The present invention relates generally to interconnecting PHY devices in a computer local area network, and more specifically to an optimized interface between an integrated repeater front-end and an integrated interface device having multiple PHY devices in such a network.
Computer networks are commonly used in today""s business environment. One common network structure uses one or more repeaters in a star topology, each repeater having several ports. A particular data packet received at one port is retransmitted to all other ports of the repeater. Each repeater restores timing and amplitude degradation of data packets received on one port and retransmits them to all other ports, and hence over the entire network. In networks employing CSMA/CD, such as an Ethernet network, every data packet passes through every repeater.
Traditional Ethernet networks (10 BASE-T) operate at 10 Mb/s. A standard promulgated by the IEEE (IEEE Standard 802.3), hereby incorporated by reference for all purposes, defines various functionality for such computer networks. Modernly, Ethernet networks are being upgraded to support 100 Mb/s operation. Standard IEEE 802.3u, hereby incorporated by reference for all purposes, defines the functionality for such high speed networks. The Standard defines operation of 100 BASE-T systems using unshielded twisted pair (UTP) physical media types. For 100 BASE-TX, the specification defines operation over 2 pairs of category 5 (CAT 5) UTP. For 100 BASE-T4, the specification defines operation over 4 pairs of Cat 3 UTP. Additionally, 802.3u includes a 100 BASE-FX specification that allows operation over dual fiber optic cabling.
The physical layer interface (PHY) defines the physical signaling scheme between two communicating devices. Many networks often use many PHY devices operating over different media types. In order to allow data terminal equipment (DTE) or a repeater to use whichever medium is more suitable, the PHY in 100 BASE-T is segregated by a Media Independent Interface (MII), which is essentially analogous to the AUI of 10 Mb/s Ethernet. In 10 Mb/s Ethernet, the AUI is an interface consisting of only six xe2x80x9cchannelsxe2x80x9d, but in 100 Mb/s operation, the interface is increased to eighteen signal xe2x80x9cchannelsxe2x80x9d in the MII. When integrated into a semiconductor device or package such as a physical housing, the channels are embodied as physical pins on the interface.
In 10 BASE-T operating at 10 Mb/s, the Ethernet/802.3 repeaters have become extremely integrated. As Ethernet has been upgraded to support 100 Mb/s operation, it has become more difficult to implement a cheap, single chip, low pin count package which houses the entire repeater functionality, especially if multiple PHY devices are integrated together.
In 100 BASE-T operation, a repeater is ideally constructed to allow some or all of its ports to be connected to any MII based PHY device. However, given the eighteen pin overhead per MII, production of integrated repeater solutions becomes more costly. A repeater front-end chip which has all MII ports for multiple PHY devices would almost certainly make the chip xe2x80x9cpad limitedxe2x80x9d. In conventional silicon processing technologies, this means that there will be so many pads for interconnect to the external device pins, that the spacing of the pads will determine the die size of the chip. Furthermore, there will be inadequate additional complexity in the logic of the chip to fill the available silicon real estate enclosed by the pad ring. Larger, more expensive chips will have to be produced to accommodate the higher pin count package which houses the entire repeater functionality. Clearly, it is desirable to reduce the pin overhead in a repeater chip, while still allowing the repeater front-end chip to connect and operate with any MII based PHY device.
The present invention provides a device for economically and efficiently interfacing a plurality of PHY devices integrated into a single semiconductor package (interface device) with an integrated repeater front-end device to produce a repeater. Making effective use of the available pins and by use of innovative design of the features of multiple integrated PHY devices, the preferred embodiment permits an effective solution that is more cost-effective than a prior art solution of simply adding additional pins. As the number of PHY devices integrated into a single package increases, the preferred embodiment of the present invention increasingly saves pin count and attendant reliability.
In the course of integrating the multiple PHY devices, a preferred embodiment of the present invention provides for an integrated device capable of having a flexibility to interoperate with any of the 100 BASE-T media types in addition to enhanced functionality. Some of these features include the ability to control transmission of security symbols for security (eavesdrop protection) using a standard MII, integration of a Carrier Integrity Monitor (CIM) state machine into the interface device to improve backward compatibility with repeater front-ends that do not implement the CIM, programmable mode control to reconfigure certain channels depending upon the environment or operational specifications. One aspect of the preferred embodiment addresses steering input ports to appropriate repeaters, such as for speed matching, load balancing or port mobility, for example. It is possible to create a dual speed repeater for 10 Mb/s and 100 Mb/s operation.
According to one aspect of the invention, it includes a first and a second PHY device for coupling to a repeater front-end. The PHY devices communicate with the repeater front-end by use of a multiplexed MII, wherein receive and transmit data channels are shared by the PHY devices and some control channels are dedicated to each PHY device.
According to another aspect of the invention, it includes a first and a second PHY for coupling to a repeater front-end, each PHY having a media independent interface. The PHY devices communicate with the repeater front-end in two different modes of operation. In one mode the PHY acts normally, while in the second mode the transmit error and receive error channels are reconfigured to operate as additional transmit and receive channels, respectively.
In yet another aspect, it includes a first PHY for coupling to a first repeater and a second PHY for coupling to a second repeater. A switch connected to both PHYs allows incoming data to one of the first and second PHYs be switched to either the first repeater of the second repeater.
A further aspect includes a PHY having a media independent interface for coupling to a repeater front-end, that operates in two modes. In one mode the collision channel operates as normal. In the second mode the collision channel is configured as a false carrier channel.
Yet a further aspect includes a security device for use with a repeater, wherein a PHY is connected to a repeater front-end. The repeater transmits a security signal to the PHY using dedicated transmit error and transmit enable channels. The PHY then responds to the received security signal by outputting a security symbol.
Another aspect includes a PHY having transmit, receive and control channels for connecting to a repeater front-end. The PHY also includes a carrier integrity monitor (CIM) for monitoring activity on the input channels of the PHY, wherein the CIM can be selectively enabled or disabled.